Some types of error correction codes, such as Low Density Parity Check (LDPC) codes, are commonly decoded using iterative decoding processes. Various decoding schemes for LDPC codes are known in the art.
For example, U.S. Pat. No. 8,473,806, whose disclosure is incorporated herein by reference, describes LDPC decoders that use reduced-complexity circular shifters that may be used to decode predefined or designed QC-LDPC codes. In addition, methods to design codes which may have particular LDPC code performance capabilities and which may operate with such decoders using reduced-complexity circular shifters are provided.
As another example, U.S. Pat. No. 8,359,522, whose disclosure is incorporated herein by reference, describes a method and a system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a Check Node Unit (CNU), the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.